Stacked (or bonded) wafers are frequently used in the semiconductor industry. One or more ultrathin wafers bonded to a carrier wafer is an example of a stacked wafer, though other semiconductor wafer designs also can be stacked wafers. For example, a stacked wafer can include a device wafer bonded to a carrier wafer. These stacked wafers can be used for both memory and logic applications. Three-dimensional integrated circuits (“3D IC”) can be produced using stacked wafers.
Stacked wafers can have complex edge profiles. The various layers of a stacked wafer can have different heights and diameters. These dimensions can be affected by the size of the various wafers prior to stacking or by processing steps. Such processing steps also can affect the edge profile of the stacked wafer, potentially even causing an undesirable edge profile.
Stacked wafers with fabrications errors can cause problems during manufacturing. For example, stacked wafers with edge profiles that do not meet specifications can pose a risk during chemical mechanical polishing (CMP), other processing steps, or wafer handling. Centricity of the stacked wafer affects the CMP process or increases handling risks. During CMP, centricity affects placement of the polishing pad with respect to the center of the stacked wafer and subsequent planarization. During wafer handling, the balance of a stacked wafer or clearance within manufacturing equipment can be affected by centricity of the stacked wafer.
Improper centricity can even ruin a stacked wafer or damage manufacturing equipment. If the stacked wafer is undercut, improperly bonded together, or contains too much glue, then the stacked wafer can break within the CMP tool, contaminating or damaging the CMP tool. Such contamination or damage leads to unwanted downtime or can even stop production within a semiconductor fab.
Furthermore, the CMP process can result in undesired edge profiles on a stacked wafer. For example, too much or not enough material may be removed during a CMP process or the CMP process may result in undercuts, overhangs, or whiskers. These undesired edge profiles can affect device yield or can impact later manufacturing steps.
Inspection can be used to identify problems with stacked wafers, but stacked wafers present unique edge inspection challenges. Undercut or other edge profiles of a stacked wafer makes it difficult to obtain scattered or reflected light in an image detector. More complicated edge profiles compound this problem. Jagged edges or complicated edge profiles also can lead to noise. For example, when a stacked wafer is stacked improperly, one side of the device wafer can have an overhang over an edge of the carrier wafer while the other side of the device wafer lies too far inside the carrier wafer. In such a situation, conventional systems can only optimize detection of the overhang or the device wafer that lies too far inside the carrier wafer. Noise and the lack of scattered or reflected light mean that improper stacking cannot be effectively analyzed.
Manual and offline edge profile measurement methods for stacked wafers are slow, time-consuming tools which provide poor quality results. These error-prone techniques can fail to accurately measure or detect flaws in stacked wafers. Furthermore, manual and offline edge profile measurement cannot be used for real-time process control during manufacturing.
There is an increasing need, especially at the back end of line (BEOL), to inspect wafers that are thinned and bonded to carriers. In some cases, these stacked wafers will not have standard edge profile shapes. Furthermore, incorrect stacking of stacked wafers can lead to loss of multiple device wafers if even one stacking step has an error. For example, the cost of one stacking fault in a hybrid memory cubicle could destroy as many as eight fully-processed device wafers.
The current solution for edge metrology is not accurate enough or fast enough for stacked wafers. Furthermore, the current solution for edge metrology may not accurately indicate when the edge profile of a stacked wafer does not match a particular model. Therefore, what is needed is an improved edge inspection technique for stacked wafers.